A common requirement of current integrated circuit manufacturing and packaging is the use of substrates to receive single or multiple integrated circuit dies as part of a semiconductor package. The substrate may be an organic build up material, a printed circuit board, a BT resin substrate, a glass or ceramic, or even a semiconductor wafer. Recently the use of three-dimensional IC (“3DIC”) packaging is increasing; and this vertically oriented approach enables stacking. Stacking of devices is done by forming vertical connections between devices. The use of through vias or through substrate vias (“TSVs”) extending through the substrate interposers is increasing with the increase in 3DIC assemblies. These through vias allow electrical coupling between integrated circuit dies and components mounted on one side of a substrate, and electrical terminals such as solder balls or solder columns mounted on the opposite side.
The assembly of integrated circuit devices on substrates creates many challenges. The substrates used may be thin. The substrates are therefore subject to warpage. Substrate warp can adversely affect later processes and device yield. The warpage may lead to interfacial mechanical strain on materials in the integrated circuit dies such as low-k dielectric materials, on solder connections such as microbumps for flip chip connections, and on solder balls for board level connections. The substrate warp also results in non-uniform bump and ball conditions, for example. The strains can lead to in-field failures after the device is put into use. The substrate warp may lead to yield problems, which are yield may be lowered due to failures that cause the devices mounted on the substrates to fail prior to completing assembly of the package.
The substrate is often used to receive one or more integrated circuit dies mounted as “flip chips”. The dies are oriented “face down” over a die side of the substrate. Solder connectors such as microbumps may be provided on the dies or the substrate. These connections provide an electrical coupling of bond pads on the integrated circuit dies to TSVs or electrical lands on the interposer. Thermal reflow is used to mount the flip chip integrated circuit dies to the substrates using the microbumps or other solder connections.
Because there is a coefficient of thermal expansion (“CTE”) mismatch between the integrated circuit dies and the other materials at the flip chip interface, an underfill is used. The underfill relieves the thermal stress that occurs as a stress or strain on the interfacial materials. The underfill may be flowed underneath the dies and surrounds the microbumps in a liquid state, and may then be cured by the use of a thermal cycle. Package substrate warp has been observed at the flip chip bond stage, and additional package warp has been noted again after underfill cure.
The package assembly process then continues by mounting a heat sink. The heat sink is a thermally conductive shield that is mounted over and in thermal contact with the top side of the integrated circuit dies. A thermally conductive material, thermal interface material (“TIM”) may be applied to the dies and the heat sink. A second thermal cycle is next performed to cure the TIM and the heat sink adhesive. Additional substrate warp has been observed following the cure of the TIM material. As the flip chip integrated circuits become larger in die area, the package warp tends to increase. Conventional approaches may fail to meet the required standards for package warp.
A continuing need thus exists for methods and apparatus to efficiently perform flip chip mounting of devices on substrates with reduced substrate warpage and reduced thermal stress, and without the problems and costs experienced when using the known methods.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.